2020.02.03 13:29:23 (1224308901438533632) from Daniel J. Bernstein:
Obvious attack that breaks the "certification" of randomness in https://www.scottaaronson.com/talks/certrand2.ppt: standard space-2^n computation of circuit state, parallelized as necessary to meet latency requirement. This attack is feasible since the "HOG" circuit verification step forces n to be small.
2020.02.03 13:41:21 (1224311913817038848) from Daniel J. Bernstein:
Scientifically, it's surprising to see the lack of citation to time-lock puzzles and verifiable delay functions, which (1) similarly hope that latency limits can stop a massively parallel attacker from outperforming the verifier, and (2) choose harder-to-parallelize computations.